The SOCoCo-80 Project

The Cat’s Out of the Bag

URL Posted

Well, I posted the URL to this blog last night on the CoCo Forums. Now the world knows what I’m working on. I guess that’s a good thing. It will motivate me to actually complete the project. This brings me to a point that I just realized last night. The direction of the project is slightly askew by definition. My original concept was to build a device to slide into the CoCo slot and drive a VGA monitor. This is a hardware/software project. However as the name implies, it has morphed into a software only project. SOC is an acronym for System On Chip.   That being said, the concept of a hardware device isn’t gone. My thinking now is to develop a SOC software version FIRST. Then when all the bugs are out, I can use the core engines to implement a hardware interface to a real 6809 (CoCo expansion slot). It would be a simple exchange to accomplish. Just remove the soft CPU and design the hardware.

I Hate Buggy Compilers

My efforts now are getting the soft CPU to run using dynamic DDR Memory. I’m realizing a few things about DDR Memory… IT SUCKS!!! Using a driver I downloaded off the internet, I find that I still need to implement a DDR state machine to access the memory. To test my knowledge of how this works, I wrote a test module in Verilog. Low and behold, it didn’t work. Night after night of changing things but still no worky.   I now get to explain why I hate buggy compilers… Last night while watching the Black Hawks get their heads handed to them, I found the problem. The DDR state machine runs on 2 clocks at 133MHz. The second clock is shifted 3 nsec. I called these clocks RAM_Clock and RAM_EClock. There’s also a PLL signal called RAM_Locked. In writing the code, I inadvertently typed RAM_Clocked instead of RAM_Clock. The stupid compiler didn’t error on the on declared variable for some reason. 4 nights of pulling my hair out because of a stupid compiler error. ARRRG!   Another point of interest on my work ethic… I have none on home projects. When I work on home projects, I’m constantly interrupted with life. So, what would normally take me a few hours to diagnose at work, takes me four days at home. Go figure.

Specification Updates

Resolution Change - I’m revising a few things on the specification. For now, I’m not going to implement any resolution higher than 800x600. There are several reasons for this. One; The original XGA specification stopped at 800x600. Second; any resolution higher than 800x600 would require a different clock frequency. The different clock frequencies can easily be generated by a PLL but would add complexity in hardware. This will be looked at further down the road. I would like to use a smaller FPGA to keep the cost down. PLL engines use large amounts of FPGA goo.

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